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Introduction To SPI Interface |
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Tutorial -
8051 Tutorial
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Written by Amol Shah
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Serial Peripheral Interface or SPI bus is a synchronous serial bus standard established by MOTOROLA. It is a 4 wire MASTER-SLAVE serial interface that operates in Full Duplex. The SPI bus can support up to 10Mbps.
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| SPI Signals |
SPI Specifies four Signals:
1) Clock: SCK/SCLK : Serial Clock (Output by Master).
2) Chip Select/Slave Select: CS/SS (active low output from Master).
3) Serial Data IN/Master Output, Slave Input: SDI/MOSI.
4) Serial Data Out/Master Input, Slave Output: SDO/MISO.
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| The SPI bus can operate with a single master device and with one or more slave devices. If the devices on the SPI bus have a chip-select signal it is possible to connect many ICs to the same SPI bus in parallel. With multiple slave devices, an independent SS signal is required from the master for each slave device. Devices have tri-state outputs that become high impedance ("disconnected") when the device is not selected, so that it does not interfere with the currently activated devices. When cascading several SPI devices, they are treated as one slave and therefore connected to the same chip select. Only one slave may talk to the master at any time, and only its SS may be activated by pulling the Slave Select LOW. |
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| cascading of several SPI devices |
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During each SPI clock cycle, a full duplex data transmission occurs:
- Master sends a bit on the MOSI line; the slave reads it from that same line.
- Slave sends a bit on the MISO line; the master reads it from that same line.
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| DISADVANTAGE OF SPI |
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1)Every IC connected to bus needs its own chip-select signal line. Thus, when 10 devices are on the bus, 10 chip-select lines, in addition to the shared clock and data lines, are needed to select the appropriate device.
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2)SPI does not have an acknowledgement mechanism to confirm receipt of data. If the SPI device is of output type then the SPI master may have no knowledge of whether a slave even exists. Basically SPI offers no hardware flow control.
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