K4H561638J-LCB3 ,256Mb, J-die DDR SDRAM, TSOP ,7.8us IC

K4H561638J-LCB3 IC

The K4H560438J  is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x 8,388,608 / 4x 4,194,304 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

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• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

• Data I/O transactions on both edges of data strobe

• Edge aligned data output, center aligned data input;

• LDM,UDM for write masking only (x16)

• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)

• Edge aligned data output, center aligned data input

Specifications of K4H561638J-LCB3 IC

•  Density: 256Mbit (32M x 8)
  

• Organization: 32M x 8
  

• Package Type: 66-TSOP (II) with lead-free packaging
  

• Data Rate: DDR-400 (400 Mb p s per pin)
  

• Voltage: 2.5V ± 0.2V
  

• Interface: SSTL_2
  

Package Includes

1 x K4H561638J-LCB3 IC, 256Mb, J-die DDR SDRAM, TSOP, 7.8us