7490 DIVIDE-BY-TWELVE AND BINARY COUNTERS
The DM7490A monolithic counter contains four masterslave
flip-flops and additional gating to provide a divide-bytwo
counter and a three-stage binary counter for which the
count cycle length is divide-by-five.
The counter has a gated zero reset and also has gated setto-nine
inputs for use in BCD nine’s complement applications.
To use the maximum count length (decade or four-bit
binary), the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical
divide-by-ten count can be obtained from the counters
by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten
square wave at output QA.