SN74155 Dual 2-Line To 4-Line Decoders, Demultiplexers

These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.

Functions Of SN74LS155: Dual 2-Line To 4-Line Decoders/Demultiplexers

• Technology Family:                             LS   
  
• VCC (Min) (V):                                        4.75   
  
• VCC (Max) (V):                                        5.25    
• Voltage (Nom) (V):                                5
• Configuration:                                       2:4  
  
• Type:                                                      Standard    
  
• IOL (Max) (mA):                                     8
  
• IOH (Max) (mA):                                   -0.4
  
• Channels:                                                2    
• Rating:                                                      Catalog    
  
• Operating Temperature Range (C):0 to 70
  
• F @ Nom Voltage (Max) (Mhz):          35
  
• ICC @ Nom Voltage (Max) (mA):       10
  
• tpd @ Nom Voltage (Max) (ns):          27
• Digital input leakage (Max) (uA):        5
  
• ESD Charged Device Model (kV):       0.75
• Bits :                                                           4
• ESD HBM (kV):                                         2

Related Links

• 74LS155 Datasheet